testbench.Structural Architecture Reference

Architecture >> testbench::Structural

Signals
clk_base	std_logic
rst_raw	std_logic
sclk_bus	std_logic
sda_bus	std_logic := ' H '
done_sig	std_logic

Instantiations
u_reloj	clk_reset_gen <Entity clk_reset_gen>
u_dut	TOP <Entity TOP>
u_sensor	mt9v111_agent <Entity mt9v111_agent>

Detailed Description

Definition at line 7 of file testbench.vhd.

Member Data Documentation

clk_base

clk_base std_logic

Definition at line 9 of file testbench.vhd.

done_sig

done_sig std_logic

Definition at line 14 of file testbench.vhd.

rst_raw

rst_raw std_logic

Definition at line 10 of file testbench.vhd.

sclk_bus

sclk_bus std_logic

Definition at line 12 of file testbench.vhd.

sda_bus

sda_bus std_logic := ' H '

Definition at line 13 of file testbench.vhd.

u_dut

u_dut TOP

Definition at line 36 of file testbench.vhd.

u_reloj

u_reloj clk_reset_gen

Definition at line 23 of file testbench.vhd.

u_sensor

u_sensor mt9v111_agent

Definition at line 45 of file testbench.vhd.

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The documentation for this design unit was generated from the following file:

• /home/runner/work/VICON/VICON/projects/vicon_cmgj/tb/testbench.vhd