Inheritance diagram for TOP:

Collaboration diagram for TOP:

Entities
TOP.Behavioral	architecture

Libraries
IEEE

Use Clauses
STD_LOGIC_1164
NUMERIC_STD

Generics
CLK_FREQ_HZ	integer := 50_000_000
I2C_FREQ_HZ	integer := 400_000
FIFO_DEPTH	integer := 16
SENSOR_ADDR	std_logic_vector ( 6 downto 0 ) := " 1011100 "

Ports
clk	in	std_logic
reset	in	std_logic
sclk	out	std_logic
sdata	inout	std_logic
done	out	std_logic

Detailed Description

Definition at line 8 of file TOP.vhd.

Member Data Documentation

◆ clk

clk in std_logic

Definition at line 16 of file TOP.vhd.

◆ CLK_FREQ_HZ

CLK_FREQ_HZ integer := 50_000_000

Definition at line 10 of file TOP.vhd.

◆ done

done out std_logic

Definition at line 21 of file TOP.vhd.

◆ FIFO_DEPTH

FIFO_DEPTH integer := 16

Definition at line 12 of file TOP.vhd.

◆ I2C_FREQ_HZ

I2C_FREQ_HZ integer := 400_000

Definition at line 11 of file TOP.vhd.

◆ IEEE

IEEE

Definition at line 5 of file TOP.vhd.

◆ NUMERIC_STD

NUMERIC_STD

Definition at line 6 of file TOP.vhd.

◆ reset

reset in std_logic

Definition at line 17 of file TOP.vhd.

◆ sclk

sclk out std_logic

Definition at line 18 of file TOP.vhd.

◆ sdata

sdata inout std_logic

Definition at line 19 of file TOP.vhd.

◆ SENSOR_ADDR

SENSOR_ADDR std_logic_vector ( 6 downto 0 ) := " 1011100 "

Definition at line 14 of file TOP.vhd.

◆ STD_LOGIC_1164

STD_LOGIC_1164