149 process(mclk)
150 begin
151 if rising_edge(mclk) then
152 if rst_final = '1' then
153 state <= ST_IDLE;
154 i2c_rw <= '0';
155 i2c_start <= '0';
156 i2c_wr_push <= '0';
157 i2c_rd_pop <= '0';
158 i2c_num_regs <= 1;
159 i2c_addr_reg <= (others => '0');
160 i2c_wr_data <= (others => '0');
161 fill_cnt <= 0;
162 rd_cnt <= 0;
163 done <= '0';
164 else
165 -- Pulsos de un ciclo por defecto
166 i2c_start <= '0';
167 i2c_wr_push <= '0';
168 i2c_rd_pop <= '0';
169
170 case state is
171
172 -----------------------------------------------------------
173 when ST_IDLE =>
174 done <= '0';
175 fill_cnt <= 0;
176 rd_cnt <= 0;
177 state <= ST_WR_FILL_FIFO;
178
179 -----------------------------------------------------------
180 -- Cargar datos en WR FIFO antes de lanzar la escritura.
181 -- Se comprueban dos condiciones: FIFO no llena y aún
182 -- quedan datos por meter.
183 -----------------------------------------------------------
184 when ST_WR_FILL_FIFO =>
185 if fill_cnt = NUM_REGS_WR then
186 -- FIFO cargada → lanzar escritura
187 fill_cnt <= 0;
188 state <= ST_WR_START;
189 elsif i2c_wr_full = '0' then
190 i2c_wr_data <= WR_DATA(fill_cnt);
191 i2c_wr_push <= '1';
192 fill_cnt <= fill_cnt + 1;
193 end if;
194 -- Si FIFO llena y aún quedan datos: esperar (raro con
195 -- FIFO_DEPTH >= NUM_REGS_WR, pero seguro)
196
197 -----------------------------------------------------------
198 when ST_WR_START =>
199 if i2c_busy = '0' then
200 i2c_rw <= '0'; -- Write
201 i2c_addr_reg <= x"04"; -- Registro inicial
202 i2c_num_regs <= NUM_REGS_WR;
203 i2c_start <= '1';
204 state <= ST_WR_WAIT;
205 end if;
206
207 -----------------------------------------------------------
208 when ST_WR_WAIT =>
209 if i2c_error = '1' then
210 state <= ST_ERROR;
211 elsif i2c_done = '1' then
212 state <= ST_RD_START;
213 end if;
214
215 -----------------------------------------------------------
216 when ST_RD_START =>
217 -- El controlador bloquea si RD FIFO no está vacía,
218 -- pero aquí sabemos que lo está (acabamos de arrancar)
219 if i2c_busy = '0' and i2c_rd_empty = '1' then
220 i2c_rw <= '1'; -- Read
221 i2c_addr_reg <= x"04";
222 i2c_num_regs <= NUM_REGS_RD;
223 i2c_start <= '1';
224 state <= ST_RD_WAIT;
225 end if;
226
227 -----------------------------------------------------------
228 when ST_RD_WAIT =>
229 if i2c_error = '1' then
230 state <= ST_ERROR;
231 elsif i2c_done = '1' then
232 rd_cnt <= 0;
233 state <= ST_RD_DRAIN;
234 end if;
235
236 -----------------------------------------------------------
237 -- Vaciar RD FIFO y guardar en buffer interno.
238 -- Cada ciclo en que rd_fifo_empty='0' se hace pop.
239 -----------------------------------------------------------
240 when ST_RD_DRAIN =>
241 if i2c_rd_empty = '0' and rd_cnt < NUM_REGS_RD then
242 i2c_rd_pop <= '1';
243 rd_buf(rd_cnt) <= i2c_rd_data;
244 rd_cnt <= rd_cnt + 1;
245 elsif rd_cnt = NUM_REGS_RD then
246 state <= ST_FINISH;
247 end if;
248
249 -----------------------------------------------------------
250 when ST_FINISH =>
251 done <= '1';
252 state <= ST_FINISH; -- Mantener done='1'
253 -- Aquí rd_buf(0) y rd_buf(1) tienen los valores leídos
254
255 -----------------------------------------------------------
256 when ST_ERROR =>
257 done <= '0';
258 state <= ST_ERROR;
259 -- Señal de error visible en i2c_error del controlador.
260 -- Añadir lógica de recuperación si es necesario.
261
262 when others =>
263 state <= ST_IDLE;
264
265 end case;
266 end if;
267 end if;
268 end process;
1.12.0