clk_reset_gen Entity Reference

Inheritance diagram for clk_reset_gen:

Entities
clk_reset_gen.Behavioral	architecture

Libraries
IEEE

Use Clauses
STD_LOGIC_1164

Ports
clk_out	out	std_logic
reset_out	out	std_logic

Detailed Description

Definition at line 4 of file clock_generator.vhd.

Member Data Documentation

clk_out

clk_out out std_logic

Definition at line 6 of file clock_generator.vhd.

IEEE

IEEE

Definition at line 2 of file clock_generator.vhd.

reset_out

reset_out out std_logic

Definition at line 8 of file clock_generator.vhd.

STD_LOGIC_1164

STD_LOGIC_1164

Definition at line 2 of file clock_generator.vhd.

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The documentation for this design unit was generated from the following file:

• /home/runner/work/VICON/VICON/projects/vicon_cmgj/tb/clock_generator.vhd