Architecture >> clk_reset_gen::Behavioral

Processes
PROCESS_1
PROCESS_2

Signals
clk_i	std_logic := ' 0 '
reset_i	std_logic := ' 1 '

Detailed Description

Definition at line 11 of file clock_generator.vhd.

Member Function/Procedure/Process Documentation

◆ PROCESS_1()

PROCESS_1 ( )

Definition at line 18 of file clock_generator.vhd.

    process
    begin
        clk_i <= '0';
        wait for 5 ns;
        clk_i <= '1';
        wait for 5 ns;
    end process;

◆ PROCESS_2()

PROCESS_2 ( )

Definition at line 27 of file clock_generator.vhd.

    process
    begin
        reset_i <= '1';    -- Activo
        wait for 100 ns;   -- Duración del reset
        reset_i <= '0';    -- Desactivado para siempre
        wait;              -- Detener proceso
    end process;

Member Data Documentation

◆ clk_i

clk_i std_logic := ' 0 '

Definition at line 12 of file clock_generator.vhd.

◆ reset_i

reset_i std_logic := ' 1 '

Definition at line 13 of file clock_generator.vhd.

The documentation for this design unit was generated from the following file:

/home/runner/work/VICON/VICON/projects/vicon_cmgj/tb/clock_generator.vhd

Processes