VICON: Sistema de Visión configurable V1.0
Trabajo Fin de Master Carlos Manuel Gomez Jimenez
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Constants | Processes | Signals | Types
i2c_master.rtl Architecture Reference
Architecture >> i2c_master::rtl

Processes

p_wr_fifo  ( clk )
p_rd_fifo  ( clk )
p_phase  ( clk )
p_fsm  ( clk )

Constants

CLKS_PER_PHASE  integer := CLK_FREQ_HZ / ( I2C_FREQ_HZ * 4 )

Types

fifo_mem_t  ( 0 to FIFO_DEPTH - 1 ) std_logic_vector ( 15 downto 0 )
state_t  ( ST_IDLE , ST_START_0 , ST_START_1 , ST_START_2 , ST_START_3 , ST_TX_0 , ST_TX_1 , ST_TX_2 , ST_TX_3 , ST_RACK_0 , ST_RACK_1 , ST_RACK_2 , ST_RACK_3 , ST_RX_0 , ST_RX_1 , ST_RX_2 , ST_RX_3 , ST_MACK_0 , ST_MACK_1 , ST_MACK_2 , ST_MACK_3 , ST_DECIDE_AFTER_ADDR_WR , ST_DECIDE_AFTER_REG_ADDR , ST_LOAD_DATA_H , ST_DECIDE_AFTER_DATA_H , ST_DECIDE_AFTER_DATA_L , ST_LOAD_NEXT_DATA_H , ST_DECIDE_AFTER_ADDR_RD , ST_DECIDE_AFTER_RX_H , ST_DECIDE_AFTER_RX_L , ST_STOP_0 , ST_STOP_1 , ST_STOP_2 , ST_STOP_3 , ST_DONE , ST_ERROR_STOP , ST_ERROR )

Signals

wr_mem  fifo_mem_t := ( others = > ( others = > ' 0 ' ) )
 Memoria de la FIFO de escritura (FIFO_DEPTH entradas de 16 bits)
wr_wr_ptr  integer range 0 to FIFO_DEPTH - 1 := 0
 Puntero de escritura de la WR FIFO.
wr_rd_ptr  integer range 0 to FIFO_DEPTH - 1 := 0
 Puntero de lectura de la WR FIFO.
wr_count  integer range 0 to FIFO_DEPTH := 0
 Número de entradas ocupadas en la WR FIFO.
wr_full_i  std_logic
 Indicador de WR FIFO llena (combinacional)
wr_empty_i  std_logic
 Indicador de WR FIFO vacía (combinacional)
wr_pop  std_logic := ' 0 '
 Pulso de pop interno de la WR FIFO (generado por la FSM)
wr_dout  std_logic_vector ( 15 downto 0 )
 Dato en la cabeza de la WR FIFO (combinacional sobre wr_rd_ptr)
rd_mem  fifo_mem_t := ( others = > ( others = > ' 0 ' ) )
 Memoria de la FIFO de lectura (FIFO_DEPTH entradas de 16 bits)
rd_wr_ptr  integer range 0 to FIFO_DEPTH - 1 := 0
 Puntero de escritura de la RD FIFO.
rd_rd_ptr  integer range 0 to FIFO_DEPTH - 1 := 0
 Puntero de lectura de la RD FIFO.
rd_count  integer range 0 to FIFO_DEPTH := 0
 Número de entradas ocupadas en la RD FIFO.
rd_full_i  std_logic
 Indicador de RD FIFO llena (combinacional)
rd_empty_i  std_logic
 Indicador de RD FIFO vacía (combinacional)
rd_push  std_logic := ' 0 '
 Pulso de push interno de la RD FIFO (generado por la FSM tras recibir un registro)
rd_din  std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
 Dato a escribir en la RD FIFO (rx_high & rx_byte)
state  state_t := ST_IDLE
seq_next  state_t := ST_IDLE
r_rw  std_logic := ' 0 '
r_addr_dev  std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
r_addr_reg  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
r_num_regs  integer range 1 to FIFO_DEPTH := 1
reg_cnt  integer range 0 to FIFO_DEPTH := 0
start_rd_mode  std_logic := ' 0 '
tx_byte  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
rx_byte  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
bit_cnt  integer range 0 to 7 := 7
wr_word  std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
rx_high  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
send_nack  std_logic := ' 0 '
phase_cnt  integer range 0 to CLKS_PER_PHASE - 1 := 0
phase_tick  std_logic := ' 0 '
scl_r  std_logic := ' 1 '
sda_out_r  std_logic := ' 1 '
sda_oe  std_logic := ' 1 '
busy_i  std_logic := ' 0 '
done_i  std_logic := ' 0 '
error_i  std_logic := ' 0 '

Detailed Description

Definition at line 74 of file i2c_controller.vhd.

Member Function/Procedure/Process Documentation

◆ p_fsm()

p_fsm ( clk  )

Definition at line 293 of file i2c_controller.vhd.

293 p_fsm : process(clk)
294 begin
295 if rising_edge(clk) then
296 if reset = '1' then
297 state <= ST_IDLE;
298 seq_next <= ST_IDLE;
299 busy_i <= '0';
300 done_i <= '0';
301 error_i <= '0';
302 scl_r <= '1';
303 sda_out_r <= '1';
304 sda_oe <= '1';
305 wr_pop <= '0';
306 rd_push <= '0';
307 rd_din <= (others => '0');
308 tx_byte <= (others => '0');
309 rx_byte <= (others => '0');
310 rx_high <= (others => '0');
311 wr_word <= (others => '0');
312 bit_cnt <= 7;
313 reg_cnt <= 0;
314 send_nack <= '0';
315 start_rd_mode <= '0';
316 r_rw <= '0';
317 r_addr_dev <= (others => '0');
318 r_addr_reg <= (others => '0');
319 r_num_regs <= 1;
320 else
321 wr_pop <= '0';
322 rd_push <= '0';
323 done_i <= '0';
324
325 case state is
326
327 -----------------------------------------------------------
328 when ST_IDLE =>
329 scl_r <= '1';
330 sda_out_r <= '1';
331 sda_oe <= '1';
332 busy_i <= '0';
333 error_i <= '0';
334 if start_i2c = '1' then
335 if rd_empty_i = '0' then
336 null; -- RD FIFO no vaciada: bloquear
337 else
338 r_rw <= rw;
339 r_addr_dev <= addr_dev;
340 r_addr_reg <= addr_reg;
341 r_num_regs <= num_regs;
342 reg_cnt <= 0;
343 start_rd_mode <= '0';
344 busy_i <= '1';
345 state <= ST_START_0;
346 end if;
347 end if;
348
349 -----------------------------------------------------------
350 -- START / Repeated START
351 -- SDA baja mientras SCL está alto → condición START
352 -----------------------------------------------------------
353 when ST_START_0 =>
354 if phase_tick = '1' then
355 scl_r <= '0'; sda_out_r <= '1'; sda_oe <= '1';
356 state <= ST_START_1;
357 end if;
358
359 when ST_START_1 =>
360 if phase_tick = '1' then
361 scl_r <= '1'; state <= ST_START_2;
362 end if;
363
364 when ST_START_2 =>
365 if phase_tick = '1' then
366 sda_out_r <= '0'; -- SDA baja con SCL alto → START
367 state <= ST_START_3;
368 end if;
369
370 when ST_START_3 =>
371 if phase_tick = '1' then
372 scl_r <= '0';
373 bit_cnt <= 7;
374 if start_rd_mode = '0' then
375 tx_byte <= r_addr_dev & '0'; -- Write
376 seq_next <= ST_DECIDE_AFTER_ADDR_WR;
377 else
378 tx_byte <= r_addr_dev & '1'; -- Read
379 seq_next <= ST_DECIDE_AFTER_ADDR_RD;
380 end if;
381 state <= ST_TX_0;
382 end if;
383
384 -----------------------------------------------------------
385 -- TX byte reutilizable
386 -- Precargar: tx_byte, bit_cnt=7, seq_next
387 -----------------------------------------------------------
388 when ST_TX_0 =>
389 if phase_tick = '1' then
390 scl_r <= '0';
391 sda_oe <= '1';
392 sda_out_r <= tx_byte(bit_cnt);
393 state <= ST_TX_1;
394 end if;
395
396 when ST_TX_1 =>
397 if phase_tick = '1' then
398 scl_r <= '1'; state <= ST_TX_2;
399 end if;
400
401 when ST_TX_2 =>
402 if phase_tick = '1' then
403 state <= ST_TX_3;
404 end if;
405
406 when ST_TX_3 =>
407 if phase_tick = '1' then
408 scl_r <= '0';
409 if bit_cnt = 0 then
410 bit_cnt <= 7;
411 state <= ST_RACK_0;
412 else
413 bit_cnt <= bit_cnt - 1;
414 state <= ST_TX_0;
415 end if;
416 end if;
417
418 -----------------------------------------------------------
419 -- RACK: ACK del esclavo (SDA='0'=ACK, '1'=NACK)
420 -----------------------------------------------------------
421 when ST_RACK_0 =>
422 if phase_tick = '1' then
423 scl_r <= '0'; sda_oe <= '0'; state <= ST_RACK_1;
424 end if;
425
426 when ST_RACK_1 =>
427 if phase_tick = '1' then
428 scl_r <= '1'; state <= ST_RACK_2;
429 end if;
430
431 when ST_RACK_2 =>
432 if phase_tick = '1' then
433 if sdata = '1' then
434 state <= ST_ERROR_STOP;
435 else
436 state <= ST_RACK_3;
437 end if;
438 end if;
439
440 when ST_RACK_3 =>
441 if phase_tick = '1' then
442 scl_r <= '0'; state <= seq_next;
443 end if;
444
445 -----------------------------------------------------------
446 -- Decisión WRITE: tras RACK de ADDR_WR → enviar REG_ADDR
447 -----------------------------------------------------------
448 when ST_DECIDE_AFTER_ADDR_WR =>
449 tx_byte <= r_addr_reg;
450 bit_cnt <= 7;
451 seq_next <= ST_DECIDE_AFTER_REG_ADDR;
452 state <= ST_TX_0;
453
454 -----------------------------------------------------------
455 -- Decisión: tras RACK de REG_ADDR
456 -- Write → capturar dato de WR FIFO, esperar un ciclo
457 -- Read → Repeated START con R/W='1'
458 -----------------------------------------------------------
459 when ST_DECIDE_AFTER_REG_ADDR =>
460 if r_rw = '0' then
461 if wr_empty_i = '0' then
462 wr_word <= wr_dout; -- capturar dato (wr_dout combinacional)
463 wr_pop <= '1'; -- avanzar puntero en el flanco siguiente
464 state <= ST_LOAD_DATA_H;
465 end if;
466 -- Si FIFO vacía: esperar en este estado
467 else
468 start_rd_mode <= '1';
469 state <= ST_START_0;
470 end if;
471
472 -----------------------------------------------------------
473 -- ST_LOAD_DATA_H: wr_word ya estable → cargar byte alto en TX
474 -----------------------------------------------------------
475 when ST_LOAD_DATA_H =>
476 tx_byte <= wr_word(15 downto 8);
477 bit_cnt <= 7;
478 seq_next <= ST_DECIDE_AFTER_DATA_H;
479 state <= ST_TX_0;
480
481 -----------------------------------------------------------
482 -- Decisión: tras RACK de DATA_H → enviar byte bajo
483 -----------------------------------------------------------
484 when ST_DECIDE_AFTER_DATA_H =>
485 tx_byte <= wr_word(7 downto 0);
486 bit_cnt <= 7;
487 seq_next <= ST_DECIDE_AFTER_DATA_L;
488 state <= ST_TX_0;
489
490 -----------------------------------------------------------
491 -- Decisión: tras RACK de DATA_L → ¿más registros?
492 -----------------------------------------------------------
493 when ST_DECIDE_AFTER_DATA_L =>
494 reg_cnt <= reg_cnt + 1;
495 if reg_cnt + 1 = r_num_regs then
496 state <= ST_STOP_0; -- todos escritos
497 else
498 -- Más registros: capturar siguiente dato
499 if wr_empty_i = '0' then
500 wr_word <= wr_dout;
501 wr_pop <= '1';
502 state <= ST_LOAD_NEXT_DATA_H;
503 end if;
504 -- Si FIFO vacía: esperar aquí
505 end if;
506
507 -----------------------------------------------------------
508 -- ST_LOAD_NEXT_DATA_H: igual que ST_LOAD_DATA_H
509 -- (estado separado para claridad; mismo comportamiento)
510 -----------------------------------------------------------
511 when ST_LOAD_NEXT_DATA_H =>
512 tx_byte <= wr_word(15 downto 8);
513 bit_cnt <= 7;
514 seq_next <= ST_DECIDE_AFTER_DATA_H;
515 state <= ST_TX_0;
516
517 -----------------------------------------------------------
518 -- Decisión READ: tras RACK de ADDR_RD → recibir DATA_H
519 -----------------------------------------------------------
520 when ST_DECIDE_AFTER_ADDR_RD =>
521 send_nack <= '0';
522 bit_cnt <= 7;
523 seq_next <= ST_DECIDE_AFTER_RX_H;
524 state <= ST_RX_0;
525
526 -----------------------------------------------------------
527 -- Decisión: tras MACK de DATA_H → recibir DATA_L
528 -- Activar NACK si este es el último registro
529 -----------------------------------------------------------
530 when ST_DECIDE_AFTER_RX_H =>
531 rx_high <= rx_byte;
532 if reg_cnt + 1 = r_num_regs then
533 send_nack <= '1'; -- último byte → NACK
534 else
535 send_nack <= '0';
536 end if;
537 bit_cnt <= 7;
538 seq_next <= ST_DECIDE_AFTER_RX_L;
539 state <= ST_RX_0;
540
541 -----------------------------------------------------------
542 -- Decisión: tras MACK de DATA_L → push RD FIFO, ¿más?
543 -----------------------------------------------------------
544 when ST_DECIDE_AFTER_RX_L =>
545 if rd_full_i = '0' then
546 rd_din <= rx_high & rx_byte;
547 rd_push <= '1';
548 reg_cnt <= reg_cnt + 1;
549 if reg_cnt + 1 = r_num_regs then
550 state <= ST_STOP_0; -- todos leídos
551 else
552 send_nack <= '0';
553 bit_cnt <= 7;
554 seq_next <= ST_DECIDE_AFTER_RX_H;
555 state <= ST_RX_0;
556 end if;
557 else
558 state <= ST_ERROR_STOP; -- RD FIFO llena
559 end if;
560
561 -----------------------------------------------------------
562 -- RX byte reutilizable
563 -- Precargar: send_nack, bit_cnt=7, seq_next
564 -----------------------------------------------------------
565 when ST_RX_0 =>
566 if phase_tick = '1' then
567 scl_r <= '0'; sda_oe <= '0'; state <= ST_RX_1;
568 end if;
569
570 when ST_RX_1 =>
571 if phase_tick = '1' then
572 scl_r <= '1'; state <= ST_RX_2;
573 end if;
574
575 when ST_RX_2 =>
576 if phase_tick = '1' then
577 rx_byte(bit_cnt) <= sdata; state <= ST_RX_3;
578 end if;
579
580 when ST_RX_3 =>
581 if phase_tick = '1' then
582 scl_r <= '0';
583 if bit_cnt = 0 then
584 bit_cnt <= 7;
585 state <= ST_MACK_0;
586 else
587 bit_cnt <= bit_cnt - 1;
588 state <= ST_RX_0;
589 end if;
590 end if;
591
592 -----------------------------------------------------------
593 -- MACK: master envía ACK ('0') o NACK ('1') según send_nack
594 -----------------------------------------------------------
595 when ST_MACK_0 =>
596 if phase_tick = '1' then
597 scl_r <= '0';
598 sda_oe <= '1';
599 sda_out_r <= send_nack;
600 state <= ST_MACK_1;
601 end if;
602
603 when ST_MACK_1 =>
604 if phase_tick = '1' then
605 scl_r <= '1'; state <= ST_MACK_2;
606 end if;
607
608 when ST_MACK_2 =>
609 if phase_tick = '1' then
610 state <= ST_MACK_3;
611 end if;
612
613 when ST_MACK_3 =>
614 if phase_tick = '1' then
615 scl_r <= '0'; state <= seq_next;
616 end if;
617
618 -----------------------------------------------------------
619 -- STOP: SDA sube mientras SCL está alto
620 -----------------------------------------------------------
621 when ST_STOP_0 =>
622 if phase_tick = '1' then
623 scl_r <= '0'; sda_out_r <= '0'; sda_oe <= '1';
624 state <= ST_STOP_1;
625 end if;
626
627 when ST_STOP_1 =>
628 if phase_tick = '1' then
629 scl_r <= '1'; state <= ST_STOP_2;
630 end if;
631
632 when ST_STOP_2 =>
633 if phase_tick = '1' then
634 sda_out_r <= '1'; -- SDA sube con SCL alto → STOP
635 state <= ST_STOP_3;
636 end if;
637
638 when ST_STOP_3 =>
639 if phase_tick = '1' then
640 state <= ST_DONE;
641 end if;
642
643 -----------------------------------------------------------
644 when ST_DONE =>
645 done_i <= '1';
646 busy_i <= '0';
647 state <= ST_IDLE;
648
649 when ST_ERROR_STOP =>
650 error_i <= '1';
651 state <= ST_STOP_0; -- liberar bus antes de volver a IDLE
652
653 when ST_ERROR =>
654 error_i <= '1';
655 busy_i <= '0';
656 state <= ST_IDLE;
657
658 when others =>
659 state <= ST_IDLE;
660
661 end case;
662 end if;
663 end if;
664 end process p_fsm;
i2c_master.rtl.rx_high
std_logic_vector( 7 downto 0) :=( others => '0') rx_high
Definition i2c_controller.vhd:175
i2c_master.rtl.phase_tick
std_logic := '0' phase_tick
Definition i2c_controller.vhd:184
i2c_master.rtl.rd_full_i
std_logic rd_full_i
Indicador de RD FIFO llena (combinacional)
Definition i2c_controller.vhd:110
i2c_master.rtl.r_addr_dev
std_logic_vector( 6 downto 0) :=( others => '0') r_addr_dev
Definition i2c_controller.vhd:156
i2c_master.rtl.tx_byte
std_logic_vector( 7 downto 0) :=( others => '0') tx_byte
Definition i2c_controller.vhd:165
i2c_master.rtl.bit_cnt
integer range 0 to 7:= 7 bit_cnt
Definition i2c_controller.vhd:167
i2c_master.rtl.rx_byte
std_logic_vector( 7 downto 0) :=( others => '0') rx_byte
Definition i2c_controller.vhd:166
i2c_master.rtl.wr_word
std_logic_vector( 15 downto 0) :=( others => '0') wr_word
Definition i2c_controller.vhd:172
i2c_master.rtl.sda_oe
std_logic := '1' sda_oe
Definition i2c_controller.vhd:191
i2c_master.rtl.state
state_t := ST_IDLE state
Definition i2c_controller.vhd:149
i2c_master.rtl.done_i
std_logic := '0' done_i
Definition i2c_controller.vhd:197
i2c_master.rtl.seq_next
state_t := ST_IDLE seq_next
Definition i2c_controller.vhd:150
i2c_master.rtl.sda_out_r
std_logic := '1' sda_out_r
Definition i2c_controller.vhd:190
i2c_master.rtl.start_rd_mode
std_logic := '0' start_rd_mode
Definition i2c_controller.vhd:162
i2c_master.rtl.send_nack
std_logic := '0' send_nack
Definition i2c_controller.vhd:178
i2c_master.rtl.wr_pop
std_logic := '0' wr_pop
Pulso de pop interno de la WR FIFO (generado por la FSM)
Definition i2c_controller.vhd:97
i2c_master.rtl.scl_r
std_logic := '1' scl_r
Definition i2c_controller.vhd:189
i2c_master.rtl.busy_i
std_logic := '0' busy_i
Definition i2c_controller.vhd:196
i2c_master.rtl.wr_empty_i
std_logic wr_empty_i
Indicador de WR FIFO vacía (combinacional)
Definition i2c_controller.vhd:95
i2c_master.rtl.rd_empty_i
std_logic rd_empty_i
Indicador de RD FIFO vacía (combinacional)
Definition i2c_controller.vhd:112
i2c_master.rtl.error_i
std_logic := '0' error_i
Definition i2c_controller.vhd:198
i2c_master.rtl.r_num_regs
integer range 1 to FIFO_DEPTH:= 1 r_num_regs
Definition i2c_controller.vhd:158
i2c_master.rtl.reg_cnt
integer range 0 to FIFO_DEPTH:= 0 reg_cnt
Definition i2c_controller.vhd:159
i2c_master.rtl.wr_dout
std_logic_vector( 15 downto 0) wr_dout
Dato en la cabeza de la WR FIFO (combinacional sobre wr_rd_ptr)
Definition i2c_controller.vhd:99
i2c_master.rtl.r_rw
std_logic := '0' r_rw
Definition i2c_controller.vhd:155
i2c_master.rtl.r_addr_reg
std_logic_vector( 7 downto 0) :=( others => '0') r_addr_reg
Definition i2c_controller.vhd:157
i2c_master.rtl.rd_din
std_logic_vector( 15 downto 0) :=( others => '0') rd_din
Dato a escribir en la RD FIFO (rx_high & rx_byte)
Definition i2c_controller.vhd:116
i2c_master.rtl.rd_push
std_logic := '0' rd_push
Pulso de push interno de la RD FIFO (generado por la FSM tras recibir un registro)
Definition i2c_controller.vhd:114
i2c_master.sdata
inout sdata std_logic
Definition i2c_controller.vhd:71
i2c_master.addr_reg
in addr_reg std_logic_vector( 7 downto 0)
Definition i2c_controller.vhd:53
i2c_master.reset
in reset std_logic
Definition i2c_controller.vhd:46
i2c_master.clk
in clk std_logic
Definition i2c_controller.vhd:45
i2c_master.rw
in rw std_logic
Definition i2c_controller.vhd:48
i2c_master.addr_dev
in addr_dev std_logic_vector( 6 downto 0)
Definition i2c_controller.vhd:52
i2c_master.start_i2c
in start_i2c std_logic
Definition i2c_controller.vhd:49
i2c_master.num_regs
in num_regs integer range 1 to FIFO_DEPTH
Definition i2c_controller.vhd:50

◆ p_phase()

p_phase ( clk  )

Definition at line 274 of file i2c_controller.vhd.

274 p_phase : process(clk)
275 begin
276 if rising_edge(clk) then
277 if reset = '1' then
278 phase_cnt <= 0;
279 phase_tick <= '0';
280 elsif phase_cnt = CLKS_PER_PHASE - 1 then
281 phase_cnt <= 0;
282 phase_tick <= '1';
283 else
284 phase_cnt <= phase_cnt + 1;
285 phase_tick <= '0';
286 end if;
287 end if;
288 end process p_phase;
i2c_master.rtl.CLKS_PER_PHASE
integer := CLK_FREQ_HZ/( I2C_FREQ_HZ* 4) CLKS_PER_PHASE
Definition i2c_controller.vhd:76
i2c_master.rtl.phase_cnt
integer range 0 to CLKS_PER_PHASE- 1:= 0 phase_cnt
Definition i2c_controller.vhd:183

◆ p_rd_fifo()

p_rd_fifo ( clk  )

Definition at line 247 of file i2c_controller.vhd.

247 p_rd_fifo : process(clk)
248 variable do_push : boolean;
249 variable do_pop : boolean;
250 begin
251 if rising_edge(clk) then
252 if reset = '1' then
253 rd_wr_ptr <= 0; rd_rd_ptr <= 0; rd_count <= 0;
254 else
255 do_push := (rd_push = '1') and (rd_full_i = '0');
256 do_pop := (rd_fifo_pop = '1') and (rd_empty_i = '0');
257 if do_push then
258 rd_mem(rd_wr_ptr) <= rd_din;
259 rd_wr_ptr <= (rd_wr_ptr + 1) mod FIFO_DEPTH;
260 end if;
261 if do_pop then
262 rd_rd_ptr <= (rd_rd_ptr + 1) mod FIFO_DEPTH;
263 end if;
264 if do_push and not do_pop then rd_count <= rd_count + 1;
265 elsif do_pop and not do_push then rd_count <= rd_count - 1;
266 end if;
267 end if;
268 end if;
269 end process p_rd_fifo;
i2c_master.rtl.rd_rd_ptr
integer range 0 to FIFO_DEPTH- 1:= 0 rd_rd_ptr
Puntero de lectura de la RD FIFO.
Definition i2c_controller.vhd:106
i2c_master.rtl.rd_wr_ptr
integer range 0 to FIFO_DEPTH- 1:= 0 rd_wr_ptr
Puntero de escritura de la RD FIFO.
Definition i2c_controller.vhd:104
i2c_master.rtl.rd_count
integer range 0 to FIFO_DEPTH:= 0 rd_count
Número de entradas ocupadas en la RD FIFO.
Definition i2c_controller.vhd:108
i2c_master.rtl.rd_mem
fifo_mem_t :=( others =>( others => '0')) rd_mem
Memoria de la FIFO de lectura (FIFO_DEPTH entradas de 16 bits)
Definition i2c_controller.vhd:102
i2c_master.rd_fifo_pop
in rd_fifo_pop std_logic
Definition i2c_controller.vhd:60
i2c_master.FIFO_DEPTH
FIFO_DEPTH integer := 16
Definition i2c_controller.vhd:43

◆ p_wr_fifo()

p_wr_fifo ( clk  )

Definition at line 214 of file i2c_controller.vhd.

214 p_wr_fifo : process(clk)
215 variable do_push : boolean;
216 variable do_pop : boolean;
217 begin
218 if rising_edge(clk) then
219 if reset = '1' then
220 wr_wr_ptr <= 0; wr_rd_ptr <= 0; wr_count <= 0;
221 else
222 do_push := (wr_fifo_push = '1') and (wr_full_i = '0');
223 do_pop := (wr_pop = '1') and (wr_empty_i = '0');
224 if do_push then
225 wr_mem(wr_wr_ptr) <= wr_fifo_data;
226 wr_wr_ptr <= (wr_wr_ptr + 1) mod FIFO_DEPTH;
227 end if;
228 if do_pop then
229 wr_rd_ptr <= (wr_rd_ptr + 1) mod FIFO_DEPTH;
230 end if;
231 if do_push and not do_pop then wr_count <= wr_count + 1;
232 elsif do_pop and not do_push then wr_count <= wr_count - 1;
233 end if;
234 end if;
235 end if;
236 end process p_wr_fifo;
i2c_master.rtl.wr_rd_ptr
integer range 0 to FIFO_DEPTH- 1:= 0 wr_rd_ptr
Puntero de lectura de la WR FIFO.
Definition i2c_controller.vhd:89
i2c_master.rtl.wr_mem
fifo_mem_t :=( others =>( others => '0')) wr_mem
Memoria de la FIFO de escritura (FIFO_DEPTH entradas de 16 bits)
Definition i2c_controller.vhd:85
i2c_master.rtl.wr_full_i
std_logic wr_full_i
Indicador de WR FIFO llena (combinacional)
Definition i2c_controller.vhd:93
i2c_master.rtl.wr_wr_ptr
integer range 0 to FIFO_DEPTH- 1:= 0 wr_wr_ptr
Puntero de escritura de la WR FIFO.
Definition i2c_controller.vhd:87
i2c_master.rtl.wr_count
integer range 0 to FIFO_DEPTH:= 0 wr_count
Número de entradas ocupadas en la WR FIFO.
Definition i2c_controller.vhd:91
i2c_master.wr_fifo_data
in wr_fifo_data std_logic_vector( 15 downto 0)
Definition i2c_controller.vhd:56
i2c_master.wr_fifo_push
in wr_fifo_push std_logic
Definition i2c_controller.vhd:55

Member Data Documentation

◆ bit_cnt

bit_cnt integer range 0 to 7 := 7

Definition at line 167 of file i2c_controller.vhd.

◆ busy_i

busy_i std_logic := ' 0 '

Definition at line 196 of file i2c_controller.vhd.

◆ CLKS_PER_PHASE

CLKS_PER_PHASE integer := CLK_FREQ_HZ / ( I2C_FREQ_HZ * 4 )

Definition at line 76 of file i2c_controller.vhd.

◆ done_i

done_i std_logic := ' 0 '

Definition at line 197 of file i2c_controller.vhd.

◆ error_i

error_i std_logic := ' 0 '

Definition at line 198 of file i2c_controller.vhd.

◆ fifo_mem_t

fifo_mem_t ( 0 to FIFO_DEPTH - 1 ) std_logic_vector ( 15 downto 0 )

Definition at line 81 of file i2c_controller.vhd.

◆ phase_cnt

phase_cnt integer range 0 to CLKS_PER_PHASE - 1 := 0

Definition at line 183 of file i2c_controller.vhd.

◆ phase_tick

phase_tick std_logic := ' 0 '

Definition at line 184 of file i2c_controller.vhd.

◆ r_addr_dev

r_addr_dev std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )

Definition at line 156 of file i2c_controller.vhd.

◆ r_addr_reg

r_addr_reg std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )

Definition at line 157 of file i2c_controller.vhd.

◆ r_num_regs

r_num_regs integer range 1 to FIFO_DEPTH := 1

Definition at line 158 of file i2c_controller.vhd.

◆ r_rw

r_rw std_logic := ' 0 '

Definition at line 155 of file i2c_controller.vhd.

◆ rd_count

rd_count integer range 0 to FIFO_DEPTH := 0

Número de entradas ocupadas en la RD FIFO.

Definition at line 108 of file i2c_controller.vhd.

◆ rd_din

rd_din std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )

Dato a escribir en la RD FIFO (rx_high & rx_byte)

Definition at line 116 of file i2c_controller.vhd.

◆ rd_empty_i

rd_empty_i std_logic

Indicador de RD FIFO vacía (combinacional)

Definition at line 112 of file i2c_controller.vhd.

◆ rd_full_i

rd_full_i std_logic

Indicador de RD FIFO llena (combinacional)

Definition at line 110 of file i2c_controller.vhd.

◆ rd_mem

rd_mem fifo_mem_t := ( others = > ( others = > ' 0 ' ) )

Memoria de la FIFO de lectura (FIFO_DEPTH entradas de 16 bits)

Definition at line 102 of file i2c_controller.vhd.

◆ rd_push

rd_push std_logic := ' 0 '

Pulso de push interno de la RD FIFO (generado por la FSM tras recibir un registro)

Definition at line 114 of file i2c_controller.vhd.

◆ rd_rd_ptr

rd_rd_ptr integer range 0 to FIFO_DEPTH - 1 := 0

Puntero de lectura de la RD FIFO.

Definition at line 106 of file i2c_controller.vhd.

◆ rd_wr_ptr

rd_wr_ptr integer range 0 to FIFO_DEPTH - 1 := 0

Puntero de escritura de la RD FIFO.

Definition at line 104 of file i2c_controller.vhd.

◆ reg_cnt

reg_cnt integer range 0 to FIFO_DEPTH := 0

Definition at line 159 of file i2c_controller.vhd.

◆ rx_byte

rx_byte std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )

Definition at line 166 of file i2c_controller.vhd.

◆ rx_high

rx_high std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )

Definition at line 175 of file i2c_controller.vhd.

◆ scl_r

scl_r std_logic := ' 1 '

Definition at line 189 of file i2c_controller.vhd.

◆ sda_oe

sda_oe std_logic := ' 1 '

Definition at line 191 of file i2c_controller.vhd.

◆ sda_out_r

sda_out_r std_logic := ' 1 '

Definition at line 190 of file i2c_controller.vhd.

◆ send_nack

send_nack std_logic := ' 0 '

Definition at line 178 of file i2c_controller.vhd.

◆ seq_next

seq_next state_t := ST_IDLE

Definition at line 150 of file i2c_controller.vhd.

◆ start_rd_mode

start_rd_mode std_logic := ' 0 '

Definition at line 162 of file i2c_controller.vhd.

◆ state

state state_t := ST_IDLE

Definition at line 149 of file i2c_controller.vhd.

◆ state_t

state_t ( ST_IDLE , ST_START_0 , ST_START_1 , ST_START_2 , ST_START_3 , ST_TX_0 , ST_TX_1 , ST_TX_2 , ST_TX_3 , ST_RACK_0 , ST_RACK_1 , ST_RACK_2 , ST_RACK_3 , ST_RX_0 , ST_RX_1 , ST_RX_2 , ST_RX_3 , ST_MACK_0 , ST_MACK_1 , ST_MACK_2 , ST_MACK_3 , ST_DECIDE_AFTER_ADDR_WR , ST_DECIDE_AFTER_REG_ADDR , ST_LOAD_DATA_H , ST_DECIDE_AFTER_DATA_H , ST_DECIDE_AFTER_DATA_L , ST_LOAD_NEXT_DATA_H , ST_DECIDE_AFTER_ADDR_RD , ST_DECIDE_AFTER_RX_H , ST_DECIDE_AFTER_RX_L , ST_STOP_0 , ST_STOP_1 , ST_STOP_2 , ST_STOP_3 , ST_DONE , ST_ERROR_STOP , ST_ERROR )

Definition at line 121 of file i2c_controller.vhd.

◆ tx_byte

tx_byte std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )

Definition at line 165 of file i2c_controller.vhd.

◆ wr_count

wr_count integer range 0 to FIFO_DEPTH := 0

Número de entradas ocupadas en la WR FIFO.

Definition at line 91 of file i2c_controller.vhd.

◆ wr_dout

wr_dout std_logic_vector ( 15 downto 0 )

Dato en la cabeza de la WR FIFO (combinacional sobre wr_rd_ptr)

Definition at line 99 of file i2c_controller.vhd.

◆ wr_empty_i

wr_empty_i std_logic

Indicador de WR FIFO vacía (combinacional)

Definition at line 95 of file i2c_controller.vhd.

◆ wr_full_i

wr_full_i std_logic

Indicador de WR FIFO llena (combinacional)

Definition at line 93 of file i2c_controller.vhd.

◆ wr_mem

wr_mem fifo_mem_t := ( others = > ( others = > ' 0 ' ) )

Memoria de la FIFO de escritura (FIFO_DEPTH entradas de 16 bits)

Definition at line 85 of file i2c_controller.vhd.

◆ wr_pop

wr_pop std_logic := ' 0 '

Pulso de pop interno de la WR FIFO (generado por la FSM)

Definition at line 97 of file i2c_controller.vhd.

◆ wr_rd_ptr

wr_rd_ptr integer range 0 to FIFO_DEPTH - 1 := 0

Puntero de lectura de la WR FIFO.

Definition at line 89 of file i2c_controller.vhd.

◆ wr_word

wr_word std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )

Definition at line 172 of file i2c_controller.vhd.

◆ wr_wr_ptr

wr_wr_ptr integer range 0 to FIFO_DEPTH - 1 := 0

Puntero de escritura de la WR FIFO.

Definition at line 87 of file i2c_controller.vhd.

The documentation for this design unit was generated from the following file: